
@article{
krish:yz97,
   Author = {Y. Zorian},
   Title = {{Fundamentals of MCM Testing and Design-for-Testability}},
   Journal = {Journal of Electronic Testing: Theory and Applications},
   Volume = {10},
      Year = {1997} }

@article{
krish:ak03,
   Author = {A. Chandra and K. Chakrabarty},
   Title = {{A unified approach to reduce SOC test data volume, scan power and testing time}},
   Journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
   Volume = {22},
   Pages = {352-362},
      Year = {2003} }

@article{
krish:lkn03,
   Author = {L. Li, K. Chakrabarty and N. A. Touba},
   Title = {{Test data compression using dictionaries with selective entries and fixed-length indices}},
   Journal = {ACM Transactions on Design Automation of Electronic Systems},
   Volume = {8},
   Pages = {470-490},
      Year = {2003} }

@article{
krish:avk04,
   Author = {A. Sehgal, V. Iyengar and K. Chakrabarty},
   Title = {{SOC test planning using virtual test access architectures}},
   Journal = {IEEE Transactions on VLSI Systems},
   Volume = {12},
   Pages = {1263-1276},
      Year = {2004} }

@article{
krish:zk07,
   Author = {Z. Wang and K. Chakrabarty},
   Title = {{Test data compression using selective encoding of scan slices}},
   Journal = {IEEE Transactions on VLSI Systems},
      Year = {2007} }

@article{
krish:ck04,
   Author = {C. Liu and K. Chakrabarty},
   Title = {{Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip}},
   Journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits Systems},
   Volume = {23},
   Pages = {1447-1459},
      Year = {2004} }


@article{
krish:Mann02,
   Author = {W. R. Mann},
   Title = {{Lecture at the IEEE Southwest Test Workshop}},
   Journal = {IEEE Southwest Test Workshop},
   url = {www.swtest.org/swtw_library/2002proc/PDF/T01_Mann.pdf},
   Year = {2002} }

@misc{itrs_2003,
author = {{Int. Technology Roadmap for Semiconductors, 2005\\http://www.itrs.net/Common/2005ITRS/Home2005.htm}},
}

@article{RS1,
author={L. Yan and J. R. English},
title={Economic cost modeling of environmental-stress-screening and
burn-in},
journal={{IEEE} Trans. Reliability},
month={Jun.},
year=1997,
volume=46,
Pages={275-282}
}

@article{DnT1,
author={P. C. Maxwell},
title={Wafer-package test mix for optimal defect detection and test time savings},
journal={{IEEE} Design and Test of Computers},
month={Sep.},
year=2003,
volume=20,
Pages={84-89}
}

@misc{Delta,
author = {{``A comparison of wafer level burn-in \& test platforms for device qualification and known good die ({KGD}) production'',\\http://www.delta-v.com/images/White\_Paper\_-\_Comparing\_WLBT\_Plat-\\forms.pdf}},
}

@article{HVST,
author={{M. F. Zakaria et al.}},
title={Reducing burn-in time through high-voltage stress test and {Weibull} statistical analysis },
journal={{IEEE} Design and Test of Computers},
month={Sep.},
year=2006,
volume=23,
Pages={88-98}
}

@book{Pat1,
author = {I. Y. Khandros and D. V. Pedersen},
title = {Wafer-level burn-in and test},
publisher = {U. S. Patent Office},
month = {May},
year = {2000},
abstract = {string macros},
note = {{Patent number 6,064,213}}
}

@InProceedings{KGD1,
author = {A.D. Singh and  P. Nigh and C. M. Krishna},
title = {Screening for known good die ({KGD}) based on defect clustering: an experimental study },
booktitle={Proc. Int. Test Conf.},
year = 1997,
pages = {362-371}
}

@InProceedings{Mot,
author = {T. Mckenzie and W. Ballouli and J. Stroupe},
title = {Wafer level burn-in and test},
booktitle={Burn-in and Test Socket Workshop},
year = 2001,
}

@article{Intel,
author={P. Tadayon},
title={Thermal challenges during microprocessor testing},
journal={Intel Technology Journal},
year=2000,
volume=Q3,
Pages={1-8}
}

@article{C1,
author={E. Larsson and K. Arvidsson and H. Fujiwara and Z. Peng},
title={Efficient test solutions for core-based designs},
journal={{IEEE} Trans. CAD},
month={May},
year=2004,
volume=23,
Pages={758-775}
}

@article{C2,
author={V. Iyengar and K. Chakrabarty and {E. J. Marinissen}},
title={Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip},
journal={Journal of Electronic Testing Theory and Applications},
month={Apr.},
year=2002,
volume=18,
Pages={213-230}
}

@InProceedings{vaasigi,
author = {A. Vassighi and O. Semenov and M. Sachdev},
title = {Thermal runaway avoidance during burn-in},
booktitle={Proc. Int. Reliability Physics Symposium},
year = 2004,
pages = {655-656}
}

@misc{P15001,
author = {{IEEE Std. 1500. IEEE Standard for Embedded Core Test - IEEE Std. 1500-2005. IEEE, New York, 2005.}},
}

@article{nicola1,
author={Q. Xu and N. Nicolici},
title={Modular {SoC} testing with reduced wrapper count},
journal={{IEEE} Trans. CAD},
month={Dec.},
year=2005,
volume=24,
Pages={1894-1908}
}

@InProceedings{goel1,
author = {S. K. Goel and E. J. Marinissen},
title = {Effective and Efficient Test Architecture Design for {SOCs}},
booktitle={Proc. Int. Test Conf.},
year = 2002,
pages = {529-538}
}

@InProceedings{Samii,
author = {{S. Samii et al.}},
title = {Cycle-accurate test power modeling and its application to SOC test scheduling},
booktitle={Proc. Int. Test Conf.},
year = 2006,
pages = {1089-3539}
}

@article{Vik_power,
author={V. Iyengar and K. Chakrabarty},
title={System-on-a-chip test scheduling with precedence relationships, preemption, and power Constraints},
journal={{IEEE} Trans. CAD},
month={Sep.},
year=2002,
volume=21,
Pages={1088-1094}
}

@Book{GT,
author = {{D. B. West}},
title = {Introduction to Graph Theory},
publisher = {Prentice Hall},
year = {2000},
}

@article{larsson_bus,
author={E. Larsson and Z. Peng},
title={ An Integrated Framework for the Design and Optimization of {SoC} Test Solutions},
journal={Journal of Electronic Testing: Theory and Applications},
month={Feb.},
year=2002,
volume=18,
Pages={385-400}
}

@Book{garey,
author = {M. Garey and D. Johnson},
title = {Computers and Intractability; A Guide to the Theory of NP-Completeness},
publisher = {W. H. Freeman},
year = {1979},
}

@misc{Advantest,
author = {{``Innovative burn-in testing for SoC devices with high power dissipation'',\\http://www.advantest.de/dasat/index.php?cid=100363\&conid=101096\&\\sid=17d2c133fab7783a035471392fd60862}},
}

@book{Pat2,
author = {P. Pochmuller},
title = {Configuration for carrying out burn-in processing operations of semiconductor devices at wafer level},
publisher = {U. S. Patent Office},
month = {Mar},
year = {2003},
abstract = {string macros},
note = {{Patent number 6,535,009}}
}

@InProceedings{Nigh,
author = {P. Nigh},
title = {Scan-based testing: The only practical solution for testing ASIC/consumer products},
booktitle={Proc. Int. Test Conf.},
year = 2002,
}

@InProceedings{pow_scan,
author = {Y. Zorian},
title = {A distributed {BIST} control scheme for complex {VLSI} devices},
booktitle={Proc. VLSI Test Symposium},
year = 1993,
pages = {4-9}
}

@article{Gupta,
author={S. Wang and S. K. Gupta},
title={An automatic test pattern generator for minimizing switching activity during scan testing activity},
journal={{IEEE} Trans. {CAD}},
month={Aug.},
year=2002,
volume=21,
Pages={954-968}
}

@article{PG2,
author={P. Girard},
title={Survey of low-power testing of {VLSI} circuits},
journal={{IEEE} Design and Test of Computers},
month={May},
year=2002,
volume=19,
Pages={80-90}
}

@InProceedings{Sankar,
author = {R. Sankaralingam and R. R. Oruganti and N. A. Touba},
title = {Static compaction techniques to control scan vector power dissipation},
booktitle={Proc. VLSI Test Symposium},
year = 2000,
pages = {35-40}
}

@InProceedings{But,
author = {{K. M. Butler et al.}},
title = {Minimizing power consumption in scan testing: pattern generation and {DFT} techniques},
booktitle={Proc. Int. Test Conf.},
year = 2004,
pages = {355-364}
}

@InProceedings{Sax,
author = {J. Saxena and K. M. Butler and L. Whetsel},
title = {An analysis of power reduction techniques in scan testing},
booktitle={Proc. Int. Test Conf.},
year = 2001,
pages = {670-677}
}

@InProceedings{XW,
author = {{X. Wen et al.}},
title = {On low-capture-power test generation for scan Testing},
booktitle={Proc. VLSI Test Symposium},
year = 2005,
pages = {265-270}
}

@article{TSP1,
author={{V. Dabholkar et al.}},
title={Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application},
journal={{IEEE} Transactions on  {Computer Aided Design}},
month={Dec.},
year=1998,
volume=17,
Pages={1325-1333}
}

@article{TSP2,
author={P. K. Latypov},
title={Energy Saving Testing of Circuits},
journal={Automation and Remote Control},
month={Apr.},
year=2001,
volume=62,
Pages={653-655}
}

@MISC{iwls2005,
    author      =   {{IWLS~2005~Benchmarks}},
    title       =   "http://iwls.org/iwls2005/benchmarks.html"
}

@article{PG2,
author={P. Girard},
title={Survey of low-power testing of {VLSI} circuits},
journal={{IEEE} Design and Test of Computers},
month={May},
year=2002,
volume=19,
Pages={80-90}
}

@InProceedings{Wund,
author = {{M.E. Imhof et al.}},
title = {Scan test planning for power reduction},
booktitle={Proc. Design Automation Conf.},
year = 2007,
pages = {521-526}
}

@article{Ros1,
author={P. M. Rosinger and B. M. Al-Hashimi and N. Nicolici},
title={Power profile manipulation: A new approach for reducing test application time under power constraints},
journal={{IEEE} Trans. CAD},
month={May},
year=2002,
volume=21,
Pages={1217-1225}
}

@InProceedings{Costa,
author = {{J. Costa et al.}},
title = {Exploiting don't cares in test patterns to reduce power during {BIST}},
booktitle={Proc. European Test Workshop},
year = 1998,
pages = {34-36}
}

@InProceedings{Ghosh,
author = {S. Ghosh and S. Basu and N. A. Touba},
title = {Joint minimization of power and area in scan testing by scan cell reordering},
booktitle={Proc. Annual Symp. on {VLSI}},
year = 2003,
pages = {246-249}
}

@InProceedings{Bash,
author = {{Z. Zhang et al.}},
title = { Enhancing delay fault coverage through low power segmented scan},
booktitle={Proc. European Test Symposium},
year = 2006,
pages = {21-28}
}

@article{Vik4,
author={V. Iyengar and K. Chakrabarty},
title={Test Bus Sizing for System-on-a-Chip},
journal={{IEEE} Trans. Computers},
month={May},
year=2005,
volume=51,
Pages={449-459}
}

@article{Mann,
author={Mann, W.R.},
title={Introduction to Wafer Level Burn-In},
journal={IEEE SW Test Workshop},
year=2002
}

@article{Pitts,
author={J. Pitts},
title={A KGD Enabler: Full Wafer Contact Technology},
journal={International KGD(Known Good Die) Package and Test Workshop},
year=2004
}

@article{MTSP,
author={{E. S. Van der Poort et al.}},
title={Solving the $k$-best traveling salesman problem},
journal={Computers and Operations Research},
month={Apr.},
year=1998,
volume=26,
Pages={409-425}
}

@Book{CE,
author = {R. Y. Rubinstein and D. P. Kroese},
title = {A Unified Approach to Combinatorial Optimization, Monte-Carlo Simulation, and Machine Learning.},
publisher = {Springer-Verlag New York, LLC},
year = {2004},
}

@misc{mentor,
author = {{``FASTSCAN and the ATPG product family'',\\http://www.mentor.com/products/dft/atpg\_compression/fastscan/}},
}

@InProceedings{Delta_IDDQ,
author = {{T. J. Powell et al.}},
title = {Delta {IDDQ} for testing reliability },
booktitle={Proc. VLSI Test Symposium},
year = 2000,
pages = {439-443}
}
